A reduction in size of circuit devices (e.g., integrated circuits (IC), transistors, flash memory, resistors, capacitors, etc.) on a semiconductor (e.g., silicon) substrate is typically a major factor considered during design, manufacture, and operation of those devices. In some cases, “scaling” may be used to “scale”down the size or scale of the devices or space from a feature of one device to the similar feature of an adjacent device. For example, during design and manufacture or forming of flash memory devices and other similar electronic devices, it is often desirable to reduce size or scale of (or between) devices, cells, transistors, bit lines (BL), and/or word lines (WL) of those devices. Such flash memory devices or cells may include polysilicon gate oxide transistor devices with floating polysilicon gates.
A n-doped flash memory cell 100 shown in FIG. 1 (Prior Art) illustrates the use of a substrate 110 comprising single crystal silicon that has been etched to form an isolation region 120 using a shallow trench isolation etch process and filled with silicon dioxide to provide electrical isolation. Floating gates 130 are formed on the active region 120 and layered with an interpolydielectric layer 140 such as a silicon oxide, silicon nitride, silicon oxide (ONO) layer stack. An n-doped control gate 150 is formed on the interpolydielectric layer 140 to provide a mechanism to enable flash memory cell operations.
As the pitch between the floating gates 130, or spacing from one floating gate 130 to another floating gate 130 decreases to support cell size reduction or ‘shrink’, it progressively becomes more difficult to dope the n-doped control gate 150 heavily enough to keep it conductive during flash memory cell operations while avoiding creation of a depletion region 160 adjacent to the interpolydielectric layer 140. A depletion region 160 is an insulating region within a conductive, doped semiconductor material where the charge carriers have diffused away, or have been forced away by an electric field.